Project Overview MIPS-R2000 Compatible Instruction Set 8 Registers, 16 Bits Wide 32 Addresses of 32 Bit Ram Word Addressable Only Writting in VHDL and able to fit on a Flex10K Board Ability to View Registers Parts of The CPU alu1.vhd [VHDL] [HTML] 1 Bit ALU alu1of.vhd [VHDL] [HTML] 1 Bit ALU With Overflow alu_n.vhd [VHDL] [HTML] N Bit ALU With Overflow clockgen.vhd [VHDL] [HTML] 3 Phase Clock Generator cpu.vhd [VHDL] [HTML] Portmapping Hell decoder.vhd [VHDL] [HTML] Decoder instreg.vhd [VHDL] [HTML] Instruction Register jaladdr.vhd [VHDL] [HTML] Jump and Link Adder Unit progctr.vhd [VHDL] [HTML] Program Counter ram.vhd [VHDL] [HTML] RAM (using LPM_RAM_DQ) regfile.vhd [VHDL] [HTML] 8x32 Register File registerOutput.vhd [VHDL] [HTML] Little Gadget to Output Registers sevenSegment.vhd [VHDL] [HTML] Seven Segment Hex Decoder shift16.vhd [VHDL] [HTML] 16 Bit Shifter shiftn_1.vhd [VHDL] [HTML] nx1 Shifter shiftn_2.vhd [VHDL] [HTML] nx2 Shifter shiftn_4.vhd [VHDL] [HTML] nx4 Shifter shiftn_8.vhd [VHDL] [HTML] nx8 Shifter wagspak.vhd [VHDL] [HTML] Package File I Used cpu.rpt [TXT] Compilation Report of CPU cs471.mif [MIF] [TXT] Memory Initialization File Timing Graphs CPU [GIF] [GIF] [GIF] [GIF] Major Problems As usual, getting myself motivated was the greatest problem that I had. Everything else went pretty smoothly after that. The ram was a little tricky conceptually, but the first solution that I tried worked out just fine. JAL caused a few problems at first because it wasn't storing the next address like it was supposed to. This was quickly fixed by the creation of Jump and Link adder unit which took care of that and some multiplexing. Assembler assembler.tar.gz [TAR.GZ] This is version 0.12 of the assembler. There are bugs that need to be fixed on it. So be forewarned. wagspat@charlie