-- Name: Clock generator which generates 3 clocks with 3-alternate-cycle sequences 
-- This code was written by Chia-Tien Dan Lo. 
-- April 28th, 1998 
-- Purpose : generate 3 clock sequences 
-- After reset signal, these clocks function like:  b -> c -> a -> b -> c ... 

library ieee; 
use ieee.std_logic_1164.all; 
USE ieee.std_logic_arith.all; 

ENTITY clockgen IS 
	PORT( clock, reset: IN STD_LOGIC; 
		clk_a, clk_b, clk_c, clk_d: OUT STD_LOGIC); 
END clockgen; 

ARCHITECTURE df OF clockgen IS
	SIGNAL temp : STD_LOGIC_VECTOR(5 DOWNTO 0); 
	SIGNAL c3Sig : STD_LOGIC;
	SIGNAL t4Sig, t3Sig : STD_LOGIC;
BEGIN
  
	p1: PROCESS(clock, reset) 
	BEGIN
		IF reset = '1' THEN
			temp <= "100000"; 
		ELSIF clock'event AND clock = '1' THEN 
			temp <= temp(0) & temp(5) & temp(4) & temp(3) & temp(2) & temp(1); 
		END IF; 
	END PROCESS; 

	t4Sig <= temp(4);
	t3Sig <= temp(1);

	WITH temp SELECT
		c3Sig <= '0' WHEN "000001" | "100000" | "010000",
			'1' WHEN OTHERS;
	clk_d <= c3Sig;
	clk_a <= temp(4); 
	clk_b <= temp(2); 
	clk_c <= temp(0); 

END df;