--
-- Patrick Wagstrom
-- cs471-001
-- instreg.vhd
--
-- instruction register
--

LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.lpm_components.all;

ENTITY instreg IS
	GENERIC (instWidth : integer := 32);
	PORT ( instIn : IN STD_LOGIC_VECTOR (instWidth - 1 DOWNTO 0);
		clock: IN STD_LOGIC;
		instOut : OUT STD_LOGIC_VECTOR (instWidth - 1 DOWNTO 0));
END instreg;

ARCHITECTURE df OF instreg IS
BEGIN
	g: lpm_ff GENERIC MAP (LPM_WIDTH => instWidth)
		PORT MAP (DATA=>instIn, clock => clock, Q=>instOut);
END df;