--
-- Patrick Wagstrom
-- CS471-001
-- 
-- Register Outputter
-- Takes a 16 bit input and a selector, decides to output the high or low bits
-- '1' outputs Hi Bits
-- '0' outputs Lo Bits
-- this is set up so in the case of a 32 bit CPU they could be cascaded to display
-- more than the 16 bits that they default to handle
--

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY registerOutput IS
	GENERIC (dataWidth : integer := 16);
	PORT (bitSelect : IN STD_LOGIC;
		dataIn : IN STD_LOGIC_VECTOR (dataWidth-1 DOWNTO 0);
		dataOut: OUT STD_LOGIC_VECTOR ((dataWidth/2)-1 DOWNTO 0));
END registerOutput;

ARCHITECTURE dataflow OF registerOutput IS
BEGIN
	WITH bitSelect SELECT
		dataOut <= dataIn(dataWidth-1 DOWNTO dataWidth/2) WHEN '1',
			dataIn((dataWidth/2)-1 DOWNTO 0) WHEN OTHERS;
END dataflow;