--
-- patrick wagstrom
-- wagspat@charlie.cns.iit.edu
-- shiftn_1.vhd
-- N bit input - 1 bit shifter
--

LIBRARY ieee;
USE ieee.std_logic_1164.all;

ENTITY shiftn_2 IS
	GENERIC (N: INTEGER := 16);
	PORT (active, r_l_shift: IN STD_LOGIC;
		data_in: IN STD_LOGIC_VECTOR (N-1 DOWNTO 0);
		data_out: OUT STD_LOGIC_VECTOR (N-1 DOWNTO 0));
END shiftn_2;

ARCHITECTURE df OF shiftn_2 IS
	SIGNAL outputSig : STD_LOGIC_VECTOR (N-1 DOWNTO 0);
BEGIN
	WITH r_l_shift SELECT
	outputSig <= "00" & data_in(N-1 DOWNTO 2) WHEN '1',
		data_in(N-3 DOWNTO 0) & "00" WHEN others;

	WITH active SELECT
	data_out <= outputSig WHEN '1',
		data_in WHEN others;
END df;